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scbs687h ? may 1997 ? revised september 2003 1 post office box 655303 ? dallas, texas 75265 support mixed-mode signal operation (5-v input and output voltages with 3.3-v v cc ) support unregulated battery operation down to 2.7 v typical v olp (output ground bounce) <0.8 v at v cc = 3.3 v, t a = 25 c i off and power-up 3-state support hot insertion bus hold on data inputs eliminates the need for external pullup/pulldown resistors latch-up performance exceeds 500 ma per jesd 17 esd protection exceeds jesd 22 ? 2000-v human-body model (a114-a) ? 200-v machine model (a115-a) sn54lvth573 ...j or w p ackage sn74lvth573 . . . db, dw, ns, or pw package (top view) sn54lvth573 . . . fk package (top view) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 oe 1d 2d 3d 4d 5d 6d 7d 8d gnd v cc 1q 2q 3q 4q 5q 6q 7q 8q le 3212019 910111213 4 5 6 7 8 18 17 16 15 14 2q 3q 4q 5q 6q 3d 4d 5d 6d 7d 2d 1d oe 8q 7q 1q 8d gnd le v cc sn74lvth573 . . . rgy package (top view) 120 10 11 2 3 4 5 6 7 8 9 19 18 17 16 15 14 13 12 1q 2q 3q 4q 5q 6q 7q 8q 1d 2d 3d 4d 5d 6d 7d 8d le v g nd cc oe description/ordering information ordering information t a package ? orderable part number top-side marking qfn ? rgy tape and reel sn74lvth573rgyr lxh573 soic ? dw tube SN74LVTH573DW lvth573 soic ? dw tape and reel SN74LVTH573DWr lvth573 sop ? ns tape and reel sn74lvth573nsr lvth573 ?40 c to 85 c ssop ? db tape and reel sn74lvth573dbr lxh573 ?40 c to 85 c tssop ? pw tube sn74lvth573pw lxh573 tssop ? pw tape and reel sn74lvth573pwr lxh573 vfbga ? gqn tape and reel sn74lvth573gqnr lxh573 vfbga ? zqn (pb-free) tape and reel sn74lvth573zqnr lxh573 cdip ? j tube snj54lvth573j snj54lvth573j ?55 c to 125 c cfp ? w tube snj54lvth573w snj54lvth573w ?55 c to 125 c lccc ? fk tube snj54lvth573fk snj54lvth573fk ? package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. copyright ? 2003, texas instruments incorporated please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
scbs687h ? may 1997 ? revised september 2003 2 post office box 655303 ? dallas, texas 75265 description/ordering information (continued) these octal latches are designed specifically for low-voltage (3.3-v) v cc operation, but with the capability to provide a ttl interface to a 5-v system environment. the eight latches of the ?lvth573 devices are transparent d-type latches. while the latch-enable (le) input is high, the q outputs follow the data (d) inputs. when le is taken low, the q outputs are latched at the logic levels set up at the d inputs. a buffered output-enable (oe ) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. in the high-impedance state, the outputs neither load nor drive the bus lines significantly. the high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. oe does not affect the internal operations of the latches. old data can be retained or new data can be entered while the outputs are in the high-impedance state. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. these devices are fully specified for hot-insertion applications using i off and power-up 3-state. the i off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. the power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. terminal assignments 1234 a 1d oe v cc 1q b 3d 3q 2d 2q c 5d 4d 5q 4q d 7d 7q 6d 6q e gnd 8d le 8q function table (each latch) inputs output oe le d output q l h h h l hl l l lx q 0 h x x z sn74lvth573 . . . gqn or zqn package (top view) 1234 a b c d e
scbs687h ? may 1997 ? revised september 2003 3 post office box 655303 ? dallas, texas 75265 logic diagram (positive logic) oe to seven other channels 1 11 2 19 le 1d c1 1d 1q pin numbers shown are for the db, dw, fk, j, ns, pw, rgy, and w packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, v cc ?0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 1) ?0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high-impedance or power-off state, v o (see note 1) ?0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high state, v o (see note 1) ?0.5 v to v cc + 0.5 v . . . . . . . . . . . . . current into any output in the low state, i o : sn54lvth573 96 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sn74lvth573 128 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . current into any output in the high state, i o (see note 2): sn54lvth573 48 ma . . . . . . . . . . . . . . . . . . . . . . . sn74lvth573 64 ma . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0) ?50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0) ?50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, ja (see note 3): db package 70 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see note 3): dw package 58 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see note 3): gqn/zqn package 78 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . (see note 3): ns package 60 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see note 3): pw package 83 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see note 4): rgy package 37 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observe d. 2. this current flows only when the output is in the high state and v o > v cc . 3. the package thermal impedance is calculated in accordance with jesd 51-7. 4. the package thermal impedance is calculated in accordance with jesd 51-5.
scbs687h ? may 1997 ? revised september 2003 4 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 5) sn54lvth573 sn74lvth573 unit min max min max unit v cc supply voltage 2.7 3.6 2.7 3.6 v v ih high-level input voltage 2 2 v v il low-level input voltage 0.8 0.8 v v i input voltage 5.5 5.5 v i oh high-level output current ?24 ?32 ma i ol low-level output current 48 64 ma ? t/ ? v input transition rise or fall rate outputs enabled 10 10 ns/v ? t/ ? v cc power-up ramp rate 200 200 s/v t a operating free-air temperature ?55 125 ?40 85 c note 5: all unused control inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004.
scbs687h ? may 1997 ? revised september 2003 5 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions sn54lvth573 sn74lvth573 unit parameter test conditions min typ ? max min typ ? max unit v ik v cc = 2.7 v, i i = ?18 ma ?1.2 ?1.2 v v cc = 2.7 v to 3.6 v, i oh = ?100 a v cc ?0.2 v cc ?0.2 v oh v cc = 2.7 v, i oh = ?8 ma 2.4 2.4 v v oh v cc = 3 v i oh = ?24 ma 2 v v cc = 3 v i oh = ?32 ma 2 v cc = 2.7 v i ol = 100 a 0.2 0.2 v cc = 2.7 v i ol = 24 ma 0.5 0.5 v ol i ol = 16 ma 0.4 0.4 v v ol v cc = 3 v i ol = 32 ma 0.5 0.5 v v cc = 3 v i ol = 48 ma 0.55 i ol = 64 ma 0.55 control inputs v cc = 0 or 3.6 v, v i = 5.5 v 10 10 i i control inputs v cc = 3.6 v, v i = v cc or gnd 1 1 a i i data inputs v cc = 3.6 v v i = v cc 1 1 a data inputs v cc = 3.6 v v i = 0 ?5 ?5 i off v cc = 0, v i or v o = 0 to 4.5 v 100 a v cc = 3 v v i = 0.8 v 75 75 i i(hold) data inputs v cc = 3 v v i = 2 v ?75 ?75 a i i(hold) data inputs v cc = 3.6 v ? , v i = 0 to 3.6 v 500 a i ozh v cc = 3.6 v, v o = 3 v 5 5 a i ozl v cc = 3.6 v, v o = 0.5 v ?5 ?5 a i ozpu v cc = 0 to 1.5 v, v o = 0.5 v to 3 v, oe = don?t care 100* 100 a i ozpd v cc = 1.5 v to 0, v o = 0.5 v to 3 v, oe = don?t care 100* 100 a v cc = 3.6 v, outputs high 0.19 0.19 i cc v cc = 3.6 v, i o = 0, v = v or gnd outputs low 5 5 ma i cc i o = 0, v i = v cc or gnd outputs disabled 0.19 0.19 ma ? i cc v cc = 3 v to 3.6 v, one input at v cc ? 0.6 v, other inputs at v cc or gnd 0.2 0.2 ma c i v i = 3 v or 0 3 3 pf c o v o = 3 v or 0 7 7 pf *on products compliant to mil-prf-38535, this parameter is not production tested. ? all typical values are at v cc = 3.3 v, t a = 25 c. ? this is the bus-hold maximum dynamic current. it is the minimum overdrive current required to switch the input from one state t o another. this is the increase in supply current for each input that is at the specified ttl voltage level, rather than v cc or gnd.
scbs687h ? may 1997 ? revised september 2003 6 post office box 655303 ? dallas, texas 75265 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see figure 1) sn54lvth573 sn74lvth573 v cc = 3.3 v 0.3 v v cc = 2.7 v v cc = 3.3 v 0.3 v v cc = 2.7 v unit min max min max min max min max t w pulse duration, le high 3 3 3 3 ns t su setup time, data before le 0.7 0.6 0.7 0.6 ns t h hold time, data after le 1.5 1.7 1.5 1.7 ns switching characteristics over recommended free-air temperature, c l = 50 pf (unless otherwise noted) (see figure 1) sn54lvth573 sn74lvth573 parameter from (input) to (output) v cc = 3.3 v 0.3 v v cc = 2.7 v v cc = 3.3 v 0.3 v v cc = 2.7 v unit (input) (output) min max min max min typ ? max min max t plh d q 1.4 4.1 4.7 1.5 2.6 3.9 4.5 ns t phl d q 1.4 4.5 4.8 1.5 2.9 3.9 4.5 ns t plh le q 1 4.4 5.4 1.9 2.9 4.2 4.9 ns t phl le q 1.4 4.4 5.1 1.9 2.9 4.2 4.9 ns t pzh oe q 1.4 5.2 6.2 1.5 3.2 5.1 5.9 ns t pzl oe q 1.4 5.2 6.2 1.5 3.9 5.1 5.9 ns t phz oe q 1.2 5.4 5.7 2 3.5 4.9 5.5 ns t plz oe q 1 5.2 5.2 2 3.2 4.6 4.9 ns ? all typical values are at v cc = 3.3 v, t a = 25 c.
scbs687h ? may 1997 ? revised september 2003 7 post office box 655303 ? dallas, texas 75265 parameter measurement information 1.5 v t h t su from output under test c l = 50 pf (see note a) load circuit s1 6 v open gnd 500 ? 500 ? data input timing input 1.5 v 2.7 v 0 v 1.5 v 1.5 v 2.7 v 0 v 2.7 v 0 v 1.5 v t w input voltage waveforms setup and hold times voltage waveforms propagation delay times inverting and noninverting outputs voltage waveforms pulse duration t plh t phl t phl t plh v oh v oh v ol v ol 1.5 v 1.5 v 2.7 v 0 v 1.5 v 1.5 v input 1.5 v output control output waveform 1 s1 at 6 v (see note b) output waveform 2 s1 at gnd (see note b) v ol v oh t pzl t pzh t plz t phz 1.5 v 1.5 v 3 v 0 v 1.5 v v ol + 0.3 v 1.5 v v oh ? 0.3 v 0 v 2.7 v voltage waveforms enable and disable times low- and high-level enabling output output t plh /t phl t plz /t pzl t phz /t pzh open 6 v gnd test s1 notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , t r 2.5 ns, t f 2.5 ns . d. the outputs are measured one at a time with one transition per measurement. e. all parameters and waveforms are not applicable to all devices. 1.5 v figure 1. load circuit and voltage waveforms
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) 5962-9583101q2a active lccc fk 20 1 tbd post-plate n / a for pkg type 5962-9583101qra active cdip j 20 1 tbd a42 snpb n / a for pkg type 5962-9583101qsa active cfp w 20 1 tbd a42 n / a for pkg type sn74lvth573dble obsolete ssop db 20 tbd call ti call ti sn74lvth573dbr active ssop db 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74lvth573dbre4 active ssop db 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVTH573DW active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVTH573DWe4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVTH573DWg4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVTH573DWr active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVTH573DWre4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN74LVTH573DWrg4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74lvth573gqnr nrnd bga mi crosta r juni or gqn 20 1000 tbd snpb level-1-240c-unlim sn74lvth573nsr active so ns 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74lvth573nsre4 active so ns 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74lvth573pw active tssop pw 20 70 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74lvth573pwe4 active tssop pw 20 70 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74lvth573pwle obsolete tssop pw 20 tbd call ti call ti sn74lvth573pwr active tssop pw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74lvth573pwre4 active tssop pw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74lvth573rgyr active qfn rgy 20 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1year sn74lvth573rgyrg4 active qfn rgy 20 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1year sn74lvth573zqnr active bga mi crosta r juni or zqn 20 1000 green (rohs & no sb/br) snagcu level-1-260c-unlim snj54lvth573fk active lccc fk 20 1 tbd post-plate n / a for pkg type snj54lvth573j active cdip j 20 1 tbd a42 snpb n / a for pkg type snj54lvth573w active cfp w 20 1 tbd a42 n / a for pkg type package option addendum www.ti.com 10-may-2007 addendum-page 1
(1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 10-may-2007 addendum-page 2
tape and reel information package materials information www.ti.com 26-apr-2007 pack materials-page 1
device package pins site reel diameter (mm) reel width (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant sn74lvth573dbr db 20 mla 330 16 8.2 7.5 2.5 12 16 q1 SN74LVTH573DWr dw 20 mla 330 24 10.8 13.0 2.7 12 24 q1 sn74lvth573gqnr gqn 20 hij 330 12 3.3 4.3 1.5 8 12 q1 sn74lvth573gqnr gqn 20 tai 330 12 3.3 4.3 1.6 8 12 q1 sn74lvth573nsr ns 20 mla 330 24 8.2 13.0 2.5 12 24 q1 sn74lvth573pwr pw 20 mla 330 16 6.95 7.1 1.6 8 16 q1 sn74lvth573rgyr rgy 20 mla 180 12 3.8 4.8 1.6 8 12 q1 sn74lvth573zqnr zqn 20 hij 330 12 3.3 4.3 1.5 8 12 q1 sn74lvth573zqnr zqn 20 tai 330 12 3.3 4.3 1.6 8 12 q1 tape and reel box information device package pins site length (mm) width (mm) height (mm) sn74lvth573dbr db 20 mla 333.2 333.2 28.58 SN74LVTH573DWr dw 20 mla 333.2 333.2 31.75 sn74lvth573gqnr gqn 20 hij 346.0 346.0 29.0 sn74lvth573gqnr gqn 20 tai 338.1 340.5 20.64 sn74lvth573nsr ns 20 mla 333.2 333.2 31.75 sn74lvth573pwr pw 20 mla 333.2 333.2 28.58 sn74lvth573rgyr rgy 20 mla 212.725 190.5 31.75 sn74lvth573zqnr zqn 20 hij 346.0 346.0 29.0 sn74lvth573zqnr zqn 20 tai 338.1 340.5 20.64 package materials information www.ti.com 26-apr-2007 pack materials-page 2
package materials information www.ti.com 26-apr-2007 pack materials-page 3

mechanical data mlcc006b october 1996 post office box 655303 ? dallas, texas 75265 fk (s-cqcc-n**) leadless ceramic chip carrier 4040140 / d 10/96 28 terminal shown b 0.358 (9,09) max (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) a no. of min max 0.358 0.660 0.761 0.458 0.342 (8,69) min (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32) (18,78) ** 20 28 52 44 68 84 0.020 (0,51) terminals 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 12 13 14 15 16 18 17 11 10 8 9 7 5 4 3 2 0.020 (0,51) 0.010 (0,25) 6 1 28 26 27 19 21 b sq a sq 22 23 24 25 20 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a metal lid. d. the terminals are gold plated. e. falls within jedec ms-004

mechanical data msso002e ? january 1995 ? revised december 2001 post office box 655303 ? dallas, texas 75265 db (r-pdso-g**) plastic small-outline 4040065 /e 12/01 28 pins shown gage plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 ? 8 0,10 0,09 0,25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150
mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
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